Broadcast-oriented wireless network-on-chip : fundamentals and feasibility

Premi extraordinari doctorat UPC curs 2015-2016, àmbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una àmplia adopció dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operació coordinada de múltiples nuclis de procés. Generacions successives han anat integrant més nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuï, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexió és un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un tràfic eminentment variable i heterogeni dels processadors amb molts nuclis. Són necessàries solucions ràpides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situació que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'ús d'arquitectures i models de programació lents, ineficients o poc programables. L'aparició de noves tecnologies d'interconnexió ha possibilitat la creació de NoCs més flexibles i escalables. En particular, la comunicació intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb tràfic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant múltiples canals sense fils per interconnectar nuclis allunyats entre sí. Aquesta estratègia és efectiva per complementar a NoCs clàssiques en escales mitjanes, però és probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales més grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al màxim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visió més àmplia on un BoWNoC serviria tràfic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades més pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball té com a objectius no només estudiar els aspectes fonamentals del paradigma BoWNoC, sinó també demostrar la seva viabilitat des dels punts de vista de la implementació, i del disseny de xarxa i arquitectura. Una exploració a la capa física valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'ús d'antenes de grafè a la banda dels terahertz ja a més llarg termini. A capa d'enllaç, la tesi aporta una anàlisi del context de l'aplicació que és, més tard, utilitzada per al disseny d'un protocol d'accés al medi que permet servir tràfic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visió híbrida és avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfície de xarxa, mostrant grans millores de rendiment per una àmplia selecció de patrons de tràfic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no només és debatut de forma qualitativa i genèrica, sinó també avaluat quantitativament per una arquitectura concreta enfocada a la sincronització. Els resultats demostren que l'impacte de BoWNoC pot anar més enllà d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version

Broadcast-oriented wireless network-on-chip : fundamentals and feasibility

Premi extraordinari doctorat UPC curs 2015-2016, àmbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una àmplia adopció dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operació coordinada de múltiples nuclis de procés. Generacions successives han anat integrant més nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuï, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexió és un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un tràfic eminentment variable i heterogeni dels processadors amb molts nuclis. Són necessàries solucions ràpides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situació que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'ús d'arquitectures i models de programació lents, ineficients o poc programables. L'aparició de noves tecnologies d'interconnexió ha possibilitat la creació de NoCs més flexibles i escalables. En particular, la comunicació intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb tràfic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant múltiples canals sense fils per interconnectar nuclis allunyats entre sí. Aquesta estratègia és efectiva per complementar a NoCs clàssiques en escales mitjanes, però és probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales més grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al màxim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visió més àmplia on un BoWNoC serviria tràfic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades més pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball té com a objectius no només estudiar els aspectes fonamentals del paradigma BoWNoC, sinó també demostrar la seva viabilitat des dels punts de vista de la implementació, i del disseny de xarxa i arquitectura. Una exploració a la capa física valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'ús d'antenes de grafè a la banda dels terahertz ja a més llarg termini. A capa d'enllaç, la tesi aporta una anàlisi del context de l'aplicació que és, més tard, utilitzada per al disseny d'un protocol d'accés al medi que permet servir tràfic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visió híbrida és avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfície de xarxa, mostrant grans millores de rendiment per una àmplia selecció de patrons de tràfic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no només és debatut de forma qualitativa i genèrica, sinó també avaluat quantitativament per una arquitectura concreta enfocada a la sincronització. Els resultats demostren que l'impacte de BoWNoC pot anar més enllà d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version

Cooperative signal amplification for molecular communication in nanonetworks.

English: Nanotechnology is enabling the development of devices in a scale ranging from a few to hundreds of nanometers. Communication between these devices greatly expands the possible applications, increasing the complexity and range of operation of the system. In particular, the resulting nanocommunication networks (or nanonetworks) show great potential for applications in the biomedical field, in which diffusion-based molecular communication is regarded as a promising alternative to electromagnetic-based solutions due to the bio-stability and energy-related requirements of this scenario. In this new paradigm, the information is encoded into pulses of molecules that reach the receiver by means of diffusion. However, molecular signals suffer a significant amount of attenuation as they propagate through the medium, thus limiting the transmission range. In this work we propose, among others, a signal amplification scheme for molecular communication nanonetworks in which a group of emitters jointly transmits a given signal after achieving synchronization by means of Quorum Sensing. By using the proposed methodology, the transmission range is extended proportionally to the number of synchronized emitters. We also provide an analytical model of Quorum Sensing, validated through simulation. This model accounts for the activation threshold (which will eventually determine the resulting amplification level) and the delay of the synchronization process.Castellano: La nanotecnología permite el desarrollo de dispositivos en una escala que va de las unidades a centenares de nanómetros. La comunicación entre estos dispositivos hace aumentar el número de aplicaciones posibles, ya que se mejora la complejidad y el rango de actuación del sistema. En concreto, las redes de nanocomunicaciones (o nanoredes) resultantes muestran un gran potencial cuando se trata de aplicaciones biomédicas, en las cuales la comunicación molecular basada en difusión de partículas supera a las soluciones electromagnéticas clásicas debido a las imposiciones energéticas y de biocompatibilidad de este escenario. En este nuevo paradigma de comunicación, la información se codifica en pulsos de moléculas que llegan al receptor gracias al fenómeno de la difusión. No obstante, las señales moleculares son sometidas a una gran atenuación a medida que se propagan a través del medio, hecho que limita severamente el alcance o rango de transmisión. En esta tesis se propone, entre otros, un esquema de amplificación de la señal para nanoredes de comunicación molecular, en el cual un grupo de emisores transmite una cierta señal de manera conjunta después de haberse sincronizado mediante la ejecución de Quorum Sensing. Con el método que proponemos, el alcance aumenta proporcionalmente al número de transmisores que se sincronizan. Además, proponemos un modelo analítico de Quorum Sensing, el cual se valida mediante simulación. Dicho modelo permite calcular el nivel umbral de activación del conjunto (hecho que determina la amplificación resultante y el rango de transmisión final) y el retardo que el proceso de sincronización introduce.Català: La nanotecnologia permet el desenvolupament de dispositius en una escala de unitats a centenars de nanòmetres. La comunicació entre aquests dispositius fa augmentar el nombre de possibles aplicacions, ja que es millora la complexitat i el rang d'actuació del sistema. En concret, les xarxes de nanocomunicacions (o nanoxarxes) resultants mostren un gran potencial quan ens referim a aplicacions biomèdiques, en les quals la comunicació molecular basada en difusió de partícules supera a les solucions de caire electromagnètic degut a les imposicions energètiques i de biocompatilitat d'aquest escenari. En aquest nou paradigma de comunicació, la informació és codificada en polsos de molècules que arriben al receptor gràcies al fenomen de la difusió. No obstant, els senyals moleculars són sotmesos a una gran atenuació a mesura que es propaguen a través del medi, fet que limita severament el rang de transmissió. En aquesta tesi es proposa, entre d'altres, un esquema d'amplificació del senyal per a nanoxarxes de comunicació molecular, en el qual un grup d'emissors transmet un cert senyal de manera conjunta després d'haver-se sincronitzat executant Quorum Sensing. Amb el mètode que proposem, l'abast o rang de transmissió augmenta proporcionalment al nombre d'emissors que se sincronitzen. A més a més, proposem un model analític de Quorum Sensing, el qual és validat mitjançant simulació. Dit model permet calcular el nivell llindar d'activació del conjunt (que de fet determina l'amplificació resultant i el rang de transmissió final) i el retard que el procés de sincronització introdueix

ProGNNosis: A data-driven model to predict GNN computation time using graph metrics

Graph Neural Networks (GNN) show great promise in problems dealing with graph-structured data. One of the unique points of GNNs is their flexibility to adapt to multiple problems, which not only leads to wide applicability, but also poses important challenges when finding the best model or acceleration technique for a particular problem. An example of such challenges resides in the fact that the accuracy or effectiveness of a GNN model or acceleration technique, respectively, generally depends on the structure of the underlying graph. In this paper, in an attempt to address the problem of graphdependent acceleration, we propose PROGNNOSIS, a data-driven model that can predict the GNN training time of a given GNN model running over a graph of arbitrary characteristics by inspecting the input graph metrics. Such prediction is made based on a regression that was previously trained offline using a diverse synthetic graph dataset. In practice, our method allows making informed decisions on which design to use for a specific problem. In the paper, the methodology to build PROGNNOSIS is defined and applied for a specific use case, where it helps to decide which graph representation is better. Our results show that PROGNNOSIS helps achieve an average speedup of 1.22× over randomly selecting a graph representation in multiple widely used GNN models such as GCN, GIN, GAT, or GraphSAGE.Peer ReviewedPostprint (author's final draft

Automata Modeling of Quorum Sensing for Nanocommunication Networks

Projecte final de carrera realitzat en col.laboració amb Broadband Wireless Networking Lab. Georgia Institute of Technology. AtlantaNanotechnology is enabling the development of devices in a scale ranging one to hundreds of nanometers. Communication between these devices underlying in the nanoscale greatly expands the possible applications, increasing the complexity and range of operation of the system. Several options for nanocommunications have been discovered and studied, and many of them take some natural mechanisms and processes as a model, or directly use di erent elements from nature to serve its purposes. For instance, in molecular communications, the information is encoded in tiny particles secreted by the emitter. In this work, a special case of molecular communications is studied and modeled. Quorum Sensing is a mechanism used by bacteria to sense their own population and coordinate or synchronize their actions, through the emission and sensing of molecules called autoinducers. The behavior of each bacterium involved featuring Quorum Sensing is modeled as an individual nite state automaton, capturing its course of action. Later, the design of a novel nanomachine that will include Quorum Sensing is presented, along with its applications. Mainly, Quorum Sensing will serve to synchronize the processes of a group of nanodevices, and this idea is developed to present \Collective Actuation Synchronization" and \Collective Actuation after Localized Sensing" nanomachines. Finally, these con gurations are implemented and simulated, and the results are later discussed

Spoofing prevention via RF power profiling in wireless network-on-chip

With increasing integration in SoCs, the Network-on-Chip (NoC) connecting of cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits of scaling of electrical wires, especially for long multi-mm distances on-chip, alternate technologies such as Wireless NoC (WNoC) have shown promise. Since WNoCs can provide low-latency one-hop transfers across the entire chip, there has been a recent surge in research demonstrating their performance and energy benefits. However, little to no work has studied the additional security challenges that are unique to WNoCs. In this work, we study the potential threat of spoofing attacks in WNoCs due to malicious hardware trojans. We introduce Veritas, a drop-in solution aimed at detecting and correcting such spoofing attacks. To this end, our solution exploits the static propagation environment of WNoCs to associate each node to a power profile. We demonstrate that, with small area and power overheads, Veritas works well in a variety of settings.Peer ReviewedPostprint (author's final draft

Error analysis of programmable metasurfaces for beam steering

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Recent years have seen the emergence of programmable metasurfaces, where the user can modify the electromagnetic (EM) response of the device via software. Adding reconfigurability to the already powerful EM capabilities of metasurfaces opens the door to novel cyber-physical systems with exciting applications in domains such as holography, cloaking, or wireless communications. This paradigm shift, however, comes with a non-trivial increase of the complexity of the metasurfaces that will pose new reliability challenges stemming from the need to integrate tuning, control, and communication resources to implement the programmability. While metasurfaces will become prone to failures, little is known about their tolerance to errors. To bridge this gap, this paper examines the reliability problem in programmable metamaterials by proposing an error model and a general methodology for error analysis. To derive the error model, the causes and potential impact of faults are identified and discussed qualitatively. The methodology is presented and exemplified for beam steering, which constitutes a relevant case for programmable metasurfaces. Results show that performance degradation depends on the type of error and its spatial distribution and that, in beam steering, error rates over 20% can still be considered acceptable.This work has been supported by the European Commission under grant H2020-FETOPEN-736876 (VISORSURF) and by ICREA under the ICREA Academia programme. The person and base station icons in Figure 1 were created by Jens Tärningand Clea Doltz from the Noun Project.Peer ReviewedPostprint (author's final draft

WiSync: an architecture for fast synchronization through on-chip wireless communication

In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support.; In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.Peer ReviewedPostprint (author's final draft

OrthoNoC: a broadcast-oriented dual-plane wireless network-on-chip architecture

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksOn-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.Peer ReviewedPostprint (author's final draft

Pulse interspersing in static multipath chip environments for Impulse Radio communications

Communications are becoming the bottleneck in the performance of Chip Multiprocessor (CMP). To address this issue, the use of wireless communications within a chip has been proposed, since they offer a low latency among nodes and high reconfigurability. The chip scenario has the particularity that is static, and the multipath can be known a priori. Within this context, we propose in this paper a simple yet very efficient modulation technique, based on Impulse Radio-On–Off-Keying (IR-OOK), which significantly optimizes the performance in Wireless Network-on-Chip (WNoC) as well as off-chip scenarios. This technique is based on interspersing information pulses among the reflected pulses in order to reduce the time between pulses, thus increasing the data rate. We prove that the final data rate can be considerably increased without increasing the hardware complexity of the transceiver.Peer ReviewedPostprint (published version